As ICs continue to decrease in size in pursuit of higher device density, higher performance, production efficiency and lowering associated costs, challenges from both fabrication and design issues have resulted in increased complexity of processing and manufacturing ICs. Conventional etching, e.g., reactive ion etching (ME), for manufacturing finFETs causes variation of fin critical dimensions (CDs) resulting in undesirable electrical properties.
Referring to FIG. 1 (a cross-sectional view), a silicon (Si) fin 101 (representing one of a plurality) is formed on a Si substrate 103. Then, a dielectric layer (not shown for illustrative convenience) is formed over the Si fin 101 and the Si substrate 103. Next, the dielectric layer is recessed, thereby exposing a top portion of the Si fin 101 above the remaining dielectric layer 105. Thereafter, an in situ steam generation (ISSG) oxidation is performed on the top portion of the Si fin 101. The ISSG oxidation grows an extended gate (EG) oxide layer 107 over the Si fin 101, which consequently thins the top portion of the Si fin 101. In this instance, the IS SG oxidation results in a CD delta between the top portion of the Si fin 101 and the bottom portion of the Si fin 101 buried under the dielectric layer 105. Since fin pitches are generally small, Si fins with bigger CDs are not properly formed during ME resulting in an embedded defect. In addition, ISSG oxide growth results in bulging of the CD of the Si fin 101 (highlighted by the circle 109), a thinner EG oxide at the foot of Si fin 101 and an uneven thickness of the EG oxide layer 107 over and on the sidewall of the Si fin 101.
A need therefore exists for methodology enabling smaller incoming fin CD with reduced bulging and thicker EG oxide at the foot of a Si fin, and a uniform EG oxide layer over and on the sidewall of the Si fin.